The present invention relates to the field of flash memories. More specifically, one embodiment of the invention provides for an improved method of preprogramming flash memory cells.
Flash memories are well known and have found many useful applications where data needs to be semi-permanently stored and retrieved quickly. See, for example, S. Aritome, et al., "Reliability Issues of Flash Memory Cells," Proceedings of the IEEE, Vol. 81, No. 5, pp. 776-787 (May 1993), which is incorporated herein by reference for all purposes. Flash memory is rewritable and retains data written thereto even in the absence of power. The ability to retain data in memory in the absence of power and the ability to rewrite that memory is provided by floating gates. A flash memory cell is typically constructed as a single field-effect transistor with a floating gate interposed between the gate of the transistor and the channel region of the transistor. By altering the charge stored on the floating gate, the state of the cell can be changed back and forth between two states, thus allowing one bit of information to be stored. The two states are referred to as an "erased" state and a "programmed" state.
In one type of flash memory, a NOR cell flash memory, all of the cells are initially in an erased state. Zero bits are written to cells by programming the individual cells, while one bits are written to the cells by erasing all of them (or a block of them) at one time.
To program a cell, charge is added to the floating gate. As the floating gate is insulated from the control gate, source and drain of the cell transistor, any charge placed on the floating gate tends to stay there. Although the floating gate is completely insulated, charge can be added and removed using techniques described below and known prior art techniques.
One way to program a cell is shown in FIG. 1. FIG. 1 shows a cell 10 with a control gate 12, a floating gate 14, a source 16 and a drain 18. Control gate 12 and floating gate 14 are separated from source 16 and drain 18, and from a substrate 20 on which they are formed, by an oxide layer 22. Suitable openings in oxide 22 are provided to allow for external connection to source 16 and drain 18. As shown, connections are provided to set Vcg (control gate voltage), Vdd (drain voltage), Vss (source voltage) and Vb (substrate voltage).
To program cell 10, the voltages are set to Vss=0v, Vdd=+6v, Vb=0v and Vcg=+12v. With a 6 volt drain-source drop, current will flow from the drain to source (with negatively charged electrons flowing in the other direction) through a channel region 26 of cell 10. An arrow 24 shows the direction of electron flow. Because of the +12v on the control gate, the electrons flowing from source 16 to drain 18 are drawn to floating gate 14. However, since channel region 26 is insulated from floating gate 14 by oxide 22, electrons cannot flow freely from active region 26 to floating gate 14. Even with the insulation, some electrons can jump from channel region 26 to floating gate 14. Those electrons are referred to as "hot electrons" as they tend to have more energy than the electrons that do not jump. Since the electrons travelling along arrow 24 gain energy as they pass through the electric field between source 16 and drain 18, the electrons nearer to drain 18 have a higher average energy and therefore the hot electrons which jump to floating gate 14 tend to be clustered about the drain junction.
To erase cell 10, the charge on floating gate 14 is removed by well known methods, such as setting Vss such that electrons jump from floating gate 14 to source 16. Overerasing cells is a known problem. With overerasing, too much charge is removed from floating gate 14, to the point where the cell is always biased on regardless of Vcg. Overerasing can occur when an already erased cell is subjected to an erasing process. If an individual cell is to be erased, one can test the individual cell and erase the cell only when the test has determined that the cell is not already erased. Of course, this is not suitable for bulk erasing.
One proposed solution to this problem is to preprogram all of the cells before subjecting the memory to a bulk erase process. See, for example, B. Dipert, et al., "Designing with FLASH MEMORY", pp. 29-30 (Annabooks, 1993). While preprogramming may overprogram some already programmed cells, overprogramming is much less of a problem than overerasing.
As it turns out, preprogramming as shown in FIG. 1 has its disadvantages. For one, preprogramming consumes considerable time and power. A typical preprogramming step for a single takes from 1 to 40 microseconds (usec) and uses from 150 to 500 microamps (uA) during that time. While this is not much for one cell (bit), it is significant when multiplied by all the cells (bits) in the memory. For example, with an 8 megabit (Mbit) memory where 8 bits might be preprogrammed at one time, the programming time is 8 Mbit * 1 usec/8=1 second, but can be as much as 40 seconds. If 8 bits are programmed at one time, the current needed is 1.2 to 4.0 milliamps over the preprogramming period, using as much as 160 milliwatts. In many applications, this is process takes too long and consumes too much power.
In order to shorten the total preprogramming time somewhat, a verify circuit is used to verify that preprogramming is successful so that the preprogramming circuit can move to the next cell as soon as a cell is preprogrammed and verified. This circuit verify uses power and also occupies chip area, which limits the chip area useable for other circuits.
Another disadvantage of the above-described preprogramming process is that the hot electron tunnelling which occurs to program floating gate 14 tends to concentrate near drain 18 and therefore resultant defects in oxide 22 tend to concentrate near the drain-channel junction, leading to premature failure of the cell.
Another form of damage is hot carrier induced leakage. This leakage happens when some of the hot carriers are trapped in the oxide between the floating gate and the active region. If enough charge is trapped after repeated program-erase cycles, the insulation will break down preventing the floating gate from holding a charge.
Therefore, an alternative to this preprogramming process is needed.